Recogni Inc., an innovator in Generative AI inference, has announced the launch of Pareto, a patented logarithmic number system designed to revolutionize AI chip design. Pareto simplifies AI computations by converting multiplications into additions, resulting in chips that are smaller, faster, and more energy-efficient.
- Product Announcement
- Recogni introduces Pareto, a logarithmic number system for AI.
- Designed to enhance AI compute efficiency by turning multiplications into additions.
- Benefits of Pareto
- Smaller Chip Size: Enables more compact chip designs, increasing compute capacity within data centers and reducing costs.
- Lower Power Consumption: Outperforms traditional FP8 and FP16 formats, providing sustainable AI computing.
- High Accuracy: Maintains less than 0.1% accuracy drop with 16-bit precision and less than 1% with 8-bit precision without the need for retraining.
- Impact on AI Models
- Addresses challenges in power consumption and computational speed associated with modern GenAI models.
- Pareto allows for significant reductions in power usage and execution time while ensuring accuracy.
- CEO’s Statement
- Marc Bolitho, CEO of Recogni, highlights Pareto’s ability to accelerate AI ambitions by reducing power consumption, latency, and chip size.
- Emphasizes Pareto as the optimal choice for modern AI chip design, balancing performance and cost-efficiency.
- Performance and Testing
- Extensive testing shows Pareto achieving over 99.9% accuracy relative to high-precision baseline models.
- Enables quick deployment of trained models with minimal accuracy loss, eliminating the need for extensive retraining.
- Developer Benefits
- Gilles Backhus, founder and VP of AI at Recogni, notes Pareto’s ability to help businesses deploy models faster and more cost-effectively.
- Pareto’s efficiency allows for high performance across all key metrics, addressing the needs of both businesses and machine learning developers.
Recogni’s Pareto represents a significant advancement in AI technology, offering a transformative approach to chip design with improved efficiency, reduced power consumption, and high accuracy. This innovation positions Pareto as a leading solution for modern AI applications and multi-modal GenAI inference.
