The AI infrastructure race is entering a new stage. As hyperscalers diversify beyond Nvidia GPUs and deploy custom accelerators of their own, the critical technology challenge is shifting from individual chip performance to the interconnect fabric that allows heterogeneous processors to work together at scale.
For years, the AI infrastructure conversation revolved around one question: Who has the fastest accelerator?
That question is becoming harder to answer—and potentially less important.
As hyperscalers deploy GPUs alongside proprietary AI accelerators, the next competitive battleground is the infrastructure connecting those processors. The ability to move data quickly between chips, servers, racks and clusters could increasingly determine how efficiently an AI system trains models or serves inference workloads.
The stakes are enormous. McKinsey estimates that global data-center capital expenditure could reach approximately $6.7 trillion by 2030, including about $5.2 trillion for facilities supporting AI workloads. Its analysis projects AI-related data-center capacity demand could reach 156 gigawatts by 2030, requiring roughly 125GW of additional capacity from 2025 onward.
That investment is creating a much larger market for the infrastructure surrounding AI accelerators. Power, cooling, memory, storage and networking all become critical as clusters grow, but interconnect technology has a particularly important role: it determines how effectively the individual pieces of compute can behave like a single system.
A new report from DIGITIMES Intelligence highlights this transition toward what can broadly be described as an AI fabric market.
The concept is relatively straightforward. AI accelerators are only useful at scale if they can exchange data efficiently. The fabric provides the high-bandwidth, low-latency connections that allow those accelerators to cooperate during model training and inference.
The architecture generally breaks into two domains: scale-up and scale-out.
Scale-up connects accelerators within a server, node or AI computing pod. It prioritizes extremely low latency and high bandwidth because processors may need to exchange data continuously during computation.
Scale-out operates at a larger level, connecting servers, racks and clusters. Distances are longer and the number of endpoints is greater, increasing the importance of bandwidth, power efficiency, signal integrity and interoperability.
The distinction is becoming more significant as AI hardware becomes less homogeneous.
Nvidia remains the dominant accelerator supplier, but hyperscalers increasingly want alternatives that can be optimized for their own workloads. Google has its TPU architecture, Amazon has Trainium and Inferentia, Microsoft has developed Maia, and Meta has pursued its own AI accelerator efforts.
The latest Google-Marvell agreement illustrates the direction of travel. In August, Google and Marvell Technology expanded a custom silicon partnership covering AI inference accelerators as well as storage, networking and memory-related components connected to Google’s TPU ecosystem.
That diversification creates a networking problem.
Different accelerators can have different memory architectures, communication requirements and software environments. An interconnect designed around one proprietary architecture may not translate efficiently to another.
This is one reason open standards are attracting attention.
The UALink Consortium is developing an open standard for AI scale-up networking. Its 200G 1.0 specification supports connections between accelerators and switches in AI computing pods, with a design capable of connecting up to 1,024 accelerators within a pod. The consortium’s 2026 specifications have expanded the technology into areas including in-network compute, chiplets and manageability.
The strategic appeal is interoperability.
If AI infrastructure becomes a collection of different accelerators rather than a single-vendor stack, cloud providers and system builders have more reason to favor technologies that reduce dependence on one hardware ecosystem.
That does not mean proprietary fabrics are disappearing. Nvidia’s networking portfolio, for example, is deeply integrated with its accelerator architecture and remains a major component of its AI platform strategy. Proprietary interconnects can offer tightly optimized performance because the chip, software and networking stack are designed together.
Open standards offer a different advantage: flexibility.
For large infrastructure operators spending billions of dollars on AI capacity, procurement flexibility can become economically significant. Being able to mix suppliers or adopt a new accelerator without redesigning the entire networking architecture can reduce vendor lock-in and potentially extend the useful life of infrastructure.
The physical layer is changing too.
Short-reach connections inside systems can continue to rely heavily on electrical signaling and copper because latency and simplicity matter. But as links extend between servers and racks, optical technologies become increasingly attractive because they can support higher bandwidth over longer distances while managing some of the power and signal-integrity challenges associated with electrical links.
That creates opportunities across a broad semiconductor and networking supply chain.
At one end are platform companies defining accelerator and switch architectures. Another layer includes suppliers of retimers, optical DSPs, connectivity controllers and electro-optical components. Beneath them are the companies producing cables, connectors, optical transceivers and other physical infrastructure.
Companies such as Broadcom, Marvell, Astera Labs and Nvidia therefore sit within a much broader AI infrastructure ecosystem in which networking silicon can become almost as strategically important as the accelerator itself.
The boundaries are already blurring. Interconnect suppliers are expanding into adjacent parts of the stack, while chip and system companies increasingly design networking capabilities around their compute architectures.
For enterprise infrastructure buyers, the implication is straightforward: AI hardware procurement can no longer be evaluated purely on accelerator specifications.
The relevant question is increasingly how efficiently a complete system moves data between compute resources.
A theoretically faster accelerator can deliver disappointing results if communication between processors becomes the bottleneck. Conversely, a heterogeneous cluster can become highly effective if its networking fabric keeps the processors sufficiently busy.
This is why AI infrastructure may increasingly resemble a systems-engineering competition rather than a chip-performance contest.
The trend is particularly relevant to Taiwan, whose semiconductor manufacturing ecosystem extends well beyond advanced processors. AI-fabric growth creates opportunities for networking chips, optical components, connectors, cables, system integration and contract manufacturing.
As data-center investment expands, the winners may therefore include companies that never manufacture an AI accelerator.
The industry’s next infrastructure race is increasingly about turning thousands of specialized processors into one coherent machine.
Market Landscape
AI infrastructure is moving toward a more heterogeneous architecture. Nvidia’s GPU platform remains a major standard, but hyperscalers are developing custom silicon to optimize performance, economics and workload control.
That diversification makes interconnect technology strategically important.
Scale-up technologies such as UALink focus on high-bandwidth accelerator-to-accelerator communication within an AI pod. UALink’s current specifications target up to 1,024 accelerators in a scale-up domain.
Scale-out networking handles communication between nodes and racks and increasingly intersects with high-speed Ethernet and optical technologies. This creates a layered market spanning switches, interconnect controllers, optical components, cables and connectors.
The competitive question is therefore shifting from which chip is fastest? to which architecture can deliver the best end-to-end performance per dollar and per watt?
For cloud providers, that means evaluating accelerator selection and networking together. For semiconductor companies, it creates opportunities beyond compute silicon. And for infrastructure operators, it raises the importance of interoperability and avoiding architectures that become difficult or expensive to upgrade.
McKinsey’s projected $5.2 trillion in AI-related data-center capital expenditure through 2030 illustrates why those architectural decisions matter. At that scale, even relatively small efficiency differences across networking, power and compute can translate into substantial operating costs.
Top Insights
- AI infrastructure is shifting toward heterogeneous compute, with GPUs and custom accelerators creating new requirements for high-bandwidth, low-latency interconnect fabrics.
- Scale-up and scale-out are becoming distinct infrastructure battles, requiring different approaches to accelerator communication, bandwidth, latency, distance and power efficiency.
- Open standards such as UALink could reduce vendor lock-in, giving hyperscalers and system builders more flexibility as alternative AI accelerator architectures emerge.
- Optical interconnects are gaining importance for larger AI clusters, as higher bandwidth and longer distances make electrical links increasingly difficult to scale efficiently.
- AI infrastructure spending creates opportunities beyond accelerators, benefiting networking silicon, optical components, cables, connectors and system manufacturers across ecosystems such as Taiwan.
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