As AI servers balloon in size and complexity, one of the least glamorous—but most critical—bottlenecks is rapidly becoming optical interconnects. THine Electronics believes it has a way around it, and it involves cutting out a major piece of the optical stack altogether.
The Japan-based fabless semiconductor company (TSE: 6769) has announced a DSP-free optical chipset for short-reach PCI Express 6 and 7 interconnects, built around its proprietary ZERO EYE SKEW® technology. The approach eliminates optical digital signal processors (DSPs) from links used in 2 TB/s PCIe 7 linear pluggable optics (LPO) and co-packaged optics (CPO)—a move THine says can reduce power consumption by 73% and cut latency by 90%.
In an era where AI infrastructure decisions are increasingly dictated by energy efficiency and nanoseconds of delay, those numbers matter.
Why DSP-Free Optical Matters
Optical DSPs have long been a necessary evil in high-speed optical links. They compensate for signal degradation, manage timing skew, and keep increasingly fast data streams usable over copper and fiber. But they also come with serious downsides: power draw, added latency, cost, and design complexity.
As AI systems scale up—rather than just scale out—those trade-offs become harder to justify.
Modern AI servers are no longer defined by a handful of accelerators. Hyperscale and enterprise AI platforms are trending toward hundreds of GPUs per system, tightly coupled with massive memory pools. According to THine, future AI servers will exceed 500 GPUs and memory devices, all requiring ultra-low-latency, high-bandwidth interconnects.
In this context, traditional DSP-based optical links start to look like architectural dead weight.
THine’s bet is that for “short-reach, slow-and-wide” connections—links that prioritize width and reliability over extreme distance—DSPs can be removed entirely, if timing alignment and signal integrity are handled correctly at the analog and mixed-signal level.
That’s where ZERO EYE SKEW® comes in.
ZERO EYE SKEW®: Timing Without the DSP
At a high level, ZERO EYE SKEW® is THine’s approach to precise timing alignment across wide parallel optical links, designed specifically for PCIe 6 and PCIe 7 workloads inside AI scale-up networks.
By tightly controlling skew across multiple lanes, THine claims it can maintain eye openings and signal margins without resorting to power-hungry optical DSPs. The result is a simpler optical link that trades digital complexity for analog precision.
This is particularly relevant for linear pluggable optics (LPO) and co-packaged optics (CPO), both of which are gaining traction as alternatives to traditional pluggables in data centers:
- LPO aims to reduce power and latency by removing DSPs from pluggable modules
- CPO pushes optics closer to compute, minimizing electrical trace lengths
Both architectures struggle with thermal budgets and signal integrity as speeds climb. Eliminating DSPs addresses both challenges at once—if it can be done reliably.
THine believes its technology makes that possible for PCIe 6 and PCIe 7, standards that are increasingly viewed as essential for next-generation AI backplanes and memory fabrics.
What THine Is Actually Shipping—and When
While the announcement is forward-looking, it includes a concrete roadmap.
THine plans to deliver:
- PCIe 6 optical DSP-free chipset samples in 2026
- PCIe 7 optical DSP-free chipset samples in 2027
The chipset includes:
- VCSEL (vertical-cavity surface-emitting laser) drivers
- Transimpedance amplifiers (TIAs)
These components form the analog heart of short-reach optical links, handling electrical-to-optical conversion and signal amplification without DSP intervention.
In parallel, THine will also sample a new “Sideband Aggregator” IC in 2026, addressing a different—but related—pain point in PCIe optical designs.
The Sideband Problem (and THine’s Fix)
High-speed optical interconnects don’t just move data lanes. They also rely on multiple sideband GPIO signals for control, monitoring, and management.
As link widths increase, the number of required sideband lines grows, complicating routing, increasing pin counts, and driving up system cost.
THine’s Sideband Aggregator IC (THCS255) tackles this by serializing and aggregating sideband signals, reducing the required GPIO lines by 50% or more using high-speed serial technology.
While less flashy than DSP elimination, this kind of integration can have a meaningful impact on board design, especially in dense AI systems where every pin, trace, and connector matters.
Taken together, the DSP-free optical chipset and sideband aggregation point to a broader theme: simplifying physical infrastructure to enable AI-scale density.
“Slow and Wide” Is the New Fast
THine repeatedly emphasizes the concept of “slow and wide” optical interconnections, a framing that may sound counterintuitive in an industry obsessed with headline speeds.
The idea is that for intra-system and rack-scale AI connectivity, raw bandwidth and latency consistency matter more than extreme reach or modulation complexity. Instead of pushing ever-higher baud rates per lane, designers can widen links and focus on reliability, power efficiency, and predictable performance.
This philosophy aligns with broader trends in AI infrastructure:
- Scale-up architectures over scale-out clusters
- Memory coherence and GPU-to-GPU bandwidth over raw network reach
- Deterministic latency for training and inference workloads
By targeting PCIe 6 and PCIe 7 specifically, THine is positioning its technology for the backplane and intra-node fabric layer—a space where Ethernet and InfiniBand don’t always fit cleanly.
Government-Backed R&D, Global Ambitions
The VCSEL drivers and TIAs were developed with support from Japan’s National Institute of Information and Communications Technology (NICT) under a national grant program, highlighting the strategic importance of optical and AI infrastructure at the state level.
But THine’s ambitions are clearly global.
The company says it is working with major global customers, hyperscalers, and partners, and plans to showcase its technology at OFC 2026 in Los Angeles—one of the most important venues for optical networking announcements.
That timing is significant. By 2026, PCIe 6 adoption is expected to accelerate, and early PCIe 7 ecosystem discussions will be well underway. Vendors that can demonstrate working silicon—not just simulations—will have a major credibility advantage.
Competitive Context: A Crowded, Power-Hungry Field
THine is not alone in pursuing DSP-lite or DSP-free optical solutions. The push toward LPO and CPO has attracted attention from:
- Optical module vendors seeking to cut power
- Hyperscalers designing custom interconnects
- Silicon providers exploring tighter analog integration
However, many approaches still rely on some form of digital compensation or assume narrower deployment scenarios.
THine’s claim of 73% power savings and 90% latency reduction—if validated in real-world systems—would put meaningful pressure on DSP-centric designs, especially in environments where thermal and energy constraints are already binding.
The challenge, as always, will be ecosystem readiness: interoperability, manufacturability, and reliability at scale.
The Bottom Line
THine’s announcement points to a future where optical links inside AI servers look less like telecom systems and more like finely tuned analog extensions of the silicon itself.
By eliminating optical DSPs for short-reach PCIe 6 and 7 connections, the company is aiming squarely at one of the hardest problems in AI infrastructure: how to scale bandwidth without scaling power, latency, and complexity at the same rate.
If ZERO EYE SKEW® delivers on its promise, THine could carve out a meaningful role in the next generation of AI scale-up architectures—where every watt saved and every nanosecond shaved off latency compounds across hundreds of accelerators.
For an industry racing toward ever-larger AI systems, that kind of efficiency may prove more valuable than raw speed alone.
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