The AI infrastructure race is creating a new challenge: designing increasingly complex chips quickly enough to keep up with demand. Synopsys and TSMC are expanding their collaboration with agentic AI design workflows, advanced EDA, chiplet optimization and silicon-proven IP aimed at accelerating the development of AI and high-performance computing systems.
Synopsys and TSMC are expanding their semiconductor-design collaboration with a set of AI-powered EDA and advanced packaging technologies designed to reduce engineering complexity across next-generation AI and HPC chips.
The collaboration combines Synopsys’ electronic design automation (EDA) software and semiconductor IP with TSMC’s advanced process nodes and packaging technologies. The objective is to connect design automation, verification, multi-die integration and silicon implementation into a more integrated development flow.
One of the most significant developments is the introduction of agentic AI into chip-design workflows.
AI Starts Designing the Chips Behind AI
Synopsys and TSMC are applying agentic AI to analog, digital and multi-die design processes. Rather than limiting AI to assistance or analysis, the workflows are designed to automate portions of complex engineering processes and optimize multiple design variables.
Synopsys’ Custom Compiler is being used to accelerate analog design migration, while Fusion Compiler incorporates LLM-assisted analysis to improve engineering productivity.
The companies are also introducing an agentic AI chiplet floorplan co-optimization flow through 3DIC Compiler. The technology automates portions of chiplet floorplanning while supporting TSMC’s 3DFabric technologies.
That capability becomes increasingly important as advanced AI processors move beyond conventional monolithic dies. Large systems can combine compute, memory and connectivity components across multiple dies, creating a much larger optimization problem involving power, thermal behavior, physical layout and communication.
Advanced Packaging Becomes a Design Problem
AI accelerators are pushing semiconductor systems toward increasingly complex packaging architectures.
Synopsys’ 3DIC Compiler can now support integrated-voltage-regulator co-design and simulation for TSMC’s CoWoS technology. Integrated voltage regulators can help address the demanding power-delivery requirements associated with high-performance multi-die systems.
The collaboration is also extending to co-packaged optics (CPO). Synopsys and TSMC are developing an integrated electronic-photonic design flow for TSMC’s COUPE technology, combining 3DIC implementation with multiphysics analysis and optimization.
Optical interconnects are attracting attention as AI systems require increasingly high-bandwidth communication between processors, memory and networking components.
IP Becomes Part of the AI Infrastructure Stack
The collaboration extends beyond EDA software. Synopsys is providing silicon-proven Interface, Foundation and Silicon Lifecycle Management IP for TSMC’s advanced processes.
The companies cite enablement and tape-out milestones on TSMC’s N2P process covering technologies including PCIe 7.0, HBM4, LPDDR6/5X/5, 224G Ethernet PHY and UCIe.
Synopsys has also demonstrated UCIe-A 32G/40G silicon on a TSMC N3P test chip using a CoWoS-S interposer and completed 64G UCIe IP tape-outs on 2nm and 3nm processes.
These technologies address different parts of the same problem: AI systems require faster memory, higher-bandwidth chip-to-chip communication and increasingly sophisticated packaging to scale compute performance.
Market Landscape
The semiconductor industry is increasingly using AI throughout the chip-development lifecycle, from architecture exploration and physical design to verification, optimization and manufacturing analysis.
Synopsys competes in EDA with companies such as Cadence and Siemens Digital Industries Software, while TSMC sits at the center of the advanced-foundry ecosystem alongside other semiconductor manufacturing providers.
At the same time, chiplet architectures and advanced packaging are changing how high-performance processors are built. Technologies such as TSMC CoWoS and 3DFabric, UCIe-based die-to-die connectivity and HBM memory are becoming important components of AI accelerator design.
The convergence of agentic EDA and advanced packaging is particularly significant because future AI systems will require optimization across multiple engineering domains simultaneously. AI-assisted design could help engineers explore that much larger design space, while human engineers remain responsible for constraints, verification and final signoff.
Top Insights
- Synopsys and TSMC are introducing agentic AI workflows that automate portions of analog, digital and chiplet design.
- Synopsys 3DIC Compiler is being used for AI-assisted chiplet floorplan co-optimization and advanced multi-die design on TSMC packaging technologies.
- The collaboration extends to integrated voltage regulators and co-packaged optics as AI systems create new power and bandwidth requirements.
- Silicon-proven IP for HBM4, PCIe 7.0, UCIe and high-speed Ethernet targets the connectivity and memory requirements of next-generation AI systems.
- The collaboration illustrates a growing feedback loop in the semiconductor industry: AI is being used to accelerate development of the hardware required to run increasingly demanding AI workloads.
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