Synopsys and Samsung Foundry Deepen Strategic Partnership to Advance AI, HPC, and Edge Chip Innovation
In a decisive move to accelerate innovation across advanced Edge AI and high-performance computing (HPC), Synopsys (Nasdaq: SNPS) and Samsung Foundry have extended their long-standing collaboration to enable rapid, efficient development of next-gen chips on Samsung’s most advanced process technologies, including SF2 and SF2P (sub-2nm nodes).
The expanded partnership integrates Synopsys’ AI-driven EDA flows, 3DIC Compiler, and comprehensive IP portfolio with Samsung’s I-CubeS™ 2.5D packaging and X-Cube technologies, allowing customers to improve power, performance, and area (PPA) while accelerating time-to-market.
“We’re enabling the most advanced AI processors—spanning from data center inference engines to ultra-efficient edge devices—by marrying best-in-class process nodes with AI-optimized design tools,” said John Koeter, SVP of IP at Synopsys.
Accelerating Edge AI, HPC, and Multi-Die Designs
The surge in Edge AI adoption—in applications ranging from smart cameras to autonomous systems—is pushing the limits of semiconductor design. Synopsys and Samsung Foundry are addressing this head-on with:
- Certified EDA flows for SF2/SF2P to streamline AI SoC design
- Multi-die packaging (I-CubeS) and automated 2.5D routing using Synopsys’ 3DIC Compiler
- Advanced IP portfolio covering UCIe, LPDDR6X, PCIe 7.0, USB4, and more
- Neural architecture and schematic migration tools for analog IP transition (SF4 → SF2)
A recent customer tape-out using Synopsys’ 3DIC Compiler and Samsung’s I-CubeS platform delivered standout results:
- HBM routing time reduced to 4 hours
- 6% improvement in eye opening for enhanced reliability and signal integrity
- Early thermal analysis and bump/TSV planning certified on Samsung’s X-Cube
“This collaboration is pushing the frontiers of design complexity while improving development speed and silicon efficiency,” said Hyung-Ock Kim, VP, Foundry Design Technology at Samsung.
Design Technology Co-Optimization and AI-Driven Flows
The alliance leverages Design Technology Co-Optimization (DTCO) to maximize SF2/SF2P node efficiency. Key highlights include:
- AI-driven flows powered by Synopsys.ai™ for digital and analog design
- Hypercells enablement for higher standard cell utilization
- Analog IP migration tools using Synopsys ASO.ai™ to shift legacy IP to new nodes
These innovations allow design teams to develop advanced SoCs optimized for power, area, and latency without compromising scalability or development speed.
Strategic IP Portfolio Integration
Synopsys’ IP catalog—optimized for Samsung Foundry processes—includes:
- Interface IP: UCIe, USB4, PCIe 7.0, LPDDR6X, 224G, MIPI
- Foundation IP: Embedded memory, logic libraries, GPIO, PVT sensors
- Security & Lifecycle IP: Including silicon lifecycle management (SLM) solutions
Together, this ecosystem empowers customers building for AI, IoT, consumer electronics, mobile, automotive, and beyond—reducing integration risk and design cycles.
Bottom Line:
By combining EDA innovation with advanced process nodes and multi-die design, Synopsys and Samsung Foundry are creating a robust foundation for the next wave of AI-optimized silicon—scalable across data center, edge, and everything in between.
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