United Microelectronics Corporation (UMC) and AP Memory are collaborating on silicon capacitor technology designed to improve power delivery in artificial intelligence (AI) and high-performance computing (HPC) systems. The partnership combines UMC’s deep trench capacitor (DTC) manufacturing technology with AP Memory’s silicon capacitor designs, targeting the growing challenge of delivering stable, efficient power to increasingly dense computing packages.
AI Chips Put Pressure on Power Delivery
As AI accelerators become more powerful and data center computing systems grow in complexity, delivering stable voltage to processors has become a critical engineering challenge. Rapid changes in workload can create fluctuations in power demand, making the design and placement of power delivery components increasingly important.
Traditional designs often rely on capacitors mounted on circuit boards to help stabilize voltage. UMC and AP Memory are targeting a different approach: placing silicon capacitors closer to the computing die, including within advanced package structures such as interposers and substrates.
Reducing the distance between power stabilization components and processors can shorten the power delivery path and improve power integrity. The goal is to help maintain stable operating conditions while supporting the electrical demands of next-generation AI and HPC systems.
The collaboration brings together two distinct capabilities. UMC contributes its deep trench capacitor technology and wafer manufacturing infrastructure, while AP Memory supplies silicon capacitor designs and system-level integration expertise. The companies aim to combine component design with scalable manufacturing as customers explore new approaches to package-level power delivery.
S-SiCap Gen2D Reaches Initial Validation
A key milestone came in the third quarter of 2026, when AP Memory’s S-SiCap Gen2D discrete silicon capacitor designs completed tape-out and initial functional validation, according to the companies.
Tape-out marks the stage at which a design is prepared for fabrication. Initial validation is an early technical checkpoint, rather than evidence that a product has completed qualification for broad commercial deployment.
The next phase will involve more comprehensive system-level performance and reliability testing of the capacitors in substrate packages. Testing is intended to assess their suitability across different capacitance and operating-voltage requirements.
Those evaluations will be important because capacitor performance depends on more than the component itself. Package layout, electrical characteristics, thermal conditions and the behavior of the wider power delivery network all affect whether a solution meets the requirements of a particular computing platform.
UMC and AP Memory are also exploring extensions beyond discrete silicon capacitors. Potential areas include capacitor-embedded interposers and landside capacitors, which could allow designers to select different integration approaches according to system architecture and packaging constraints.
The companies have not disclosed commercial shipment dates, production volumes, pricing or quantified improvements in power efficiency. Those details will help determine how quickly the technology could move from validation into broader use.
Advanced Packaging Becomes Part of the Power Strategy
The collaboration reflects a broader shift in semiconductor engineering: power delivery is increasingly being addressed at the package level, rather than treated solely as a motherboard design problem.
AI accelerators and HPC processors combine high transistor density with substantial and rapidly changing power requirements. As these systems scale, engineers must manage voltage stability, electrical losses, heat and the physical space available for supporting components. Moving capacitors closer to the processor can help address some of these constraints, although the benefits depend on the package design and system implementation.
Deep trench capacitor technology uses high-aspect-ratio structures formed in silicon to achieve high capacitance within a compact footprint. This makes it relevant to designs where space is limited and power integrity is critical. Integrating such components into advanced packages, however, introduces manufacturing and reliability requirements that must be evaluated alongside electrical performance.
UMC is positioning its DTC capabilities as part of a wider power delivery roadmap spanning discrete and embedded silicon capacitors, internal voltage regulators and advanced packaging. The company also says it is investing in manufacturing capacity for power delivery and heterogeneous integration solutions.
For AP Memory, the partnership offers a route to manufacture its S-SiCap designs using UMC’s foundry capabilities. The companies describe the collaboration as a solution spanning product design and wafer manufacturing, but broader adoption will depend on qualification results and compatibility with customers’ specific package architectures.
What the Collaboration Means for AI Infrastructure
The partnership highlights how the AI infrastructure supply chain is expanding beyond processors, memory and conventional packaging. Specialized power components are becoming another area of development as chipmakers and system designers work to improve the electrical performance of dense computing systems.
The immediate milestone is technical rather than commercial: S-SiCap Gen2D has completed tape-out and initial functional validation, with system-level testing still ahead. Reliability data, manufacturability at scale and performance within real package configurations will be central to assessing its readiness.
The companies are also considering additional capacitor formats, suggesting that they intend to address more than one system design. If the solutions pass validation and gain customer adoption, they could give package designers more options for locating power stabilization components closer to high-demand compute devices.
For now, UMC and AP Memory have established a development and manufacturing collaboration with a defined next step. The extent of its impact on AI system power efficiency will become clearer as the technology progresses through qualification and customer-level evaluation.
Market Landscape
Power delivery is becoming a key design consideration in AI and HPC infrastructure. As computing packages become more complex, engineers are evaluating ways to reduce electrical path lengths, improve voltage stability and integrate supporting components within increasingly constrained package footprints.
Silicon capacitors and embedded power components are part of this shift toward closer integration between compute and power delivery. Their practical value depends on validated electrical performance, reliability, manufacturing yield and the needs of each system architecture. UMC and AP Memory’s collaboration addresses these requirements through a combination of capacitor design, foundry manufacturing and advanced packaging expertise.
Top Insights
- UMC and AP Memory are collaborating on silicon capacitor solutions intended to improve power delivery for AI and high-performance computing systems.
- AP Memory’s S-SiCap Gen2D designs completed tape-out and initial functional validation in the third quarter of 2026.
- The next development phase involves system-level performance and reliability testing in substrate packages.
- The companies are exploring capacitor-embedded interposers and landside capacitors to support different computing system architectures.
- UMC’s broader roadmap includes discrete and embedded capacitors, internal voltage regulators and advanced packaging for power integration.
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