d-Matrix, a pioneer in generative AI inference compute for data centers, has chosen the AndesCore™ AX46MPV as the control and vector compute engine for its upcoming Raptor™ inference platform. Andes Technology (SIN: US03420C2089; ISIN: US03420C1099), a leading provider of high-efficiency, low-power RISC-V processor IP and a Founding Premier member of RISC-V International, announced the collaboration today.
The partnership unites d-Matrix’s memory-centric compute innovation with Andes’ open-standard RISC-V architecture, bringing new performance and energy-efficiency breakthroughs to data center–scale AI inference.
Advancing 3D In-Memory Compute for Generative AI
The new Raptor accelerator will be the first platform built on d-Matrix’s 3D In-Memory Compute (3DIMC™) technology—the industry’s first 3D DRAM-based, chiplet-driven architecture purpose-built for AI inference at scale. By stacking compute and memory in a 3D topology, 3DIMC reduces data-movement energy and latency by an order of magnitude, directly addressing the “memory wall” bottleneck that limits conventional inference architectures.
Andes AX46MPV as Orchestration and Vector Compute Engine
Within Raptor, the Andes AX46MPV acts as both orchestration CPU and vector compute engine. The processor manages workload scheduling, memory coordination, and runtime control across the accelerator’s high-bandwidth compute fabric, while also accelerating compute tasks such as activation functions.
“Raptor’s innovative design is pushing inference efficiency and scalability far beyond what conventional architectures can achieve,” said Sid Sheth, Founder and CEO of d-Matrix. “The AX46MPV’s RISC-V architecture provides the ideal CPU for our 3DIMC approach, enabling unprecedented performance per watt for data center–scale AI.”
“Our collaboration with d-Matrix showcases how RISC-V is enabling true datacenter-class inference systems,” said Frankwell Lin, Chairman and CEO of Andes Technology. “By combining d-Matrix’s groundbreaking 3DIMC architecture with Andes’ advanced vector RISC-V CPUs, we’re powering the next generation of generative AI inference.”
Strengthening RISC-V Momentum in AI Infrastructure
The partnership marks a new milestone for the expansion of RISC-V into large-scale AI infrastructure. It pairs Andes’ mature CPU IP and software ecosystem with d-Matrix’s chiplet-based, memory-centric architecture to deliver new levels of performance-per-watt and total cost of ownership (TCO) for enterprise AI deployments.
Technology Highlights
The AX46MPV is a 64-bit, Linux-capable multicore RISC-V CPU IP featuring:
- Up to 2048-bit Vector Processing Unit (RVV 1.0)
- Enhanced reduction-sum operations for transformer workloads
- Dual load-store units supporting flexible scalar/vector operations
- High-bandwidth Vector Memory (HVM) for out-of-order data return handling
- A large number of outstanding bus requests for higher throughput
Reference kernels central to LLM and transformer operations show up to 2.3× performance improvement over its predecessor, the AX45MPV.
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